Core parallel execution with different optimization characteristics to decrease dynamic execution path
US7028167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2002 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Oct 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a processor with two or more parallel instruction paths for processing instructions. The instruction paths may be implemented with a plurality of cores on a common die. Instructions of the invention are preferably processed within a bundle of two or more instructions of a common program thread; and each of the instruction paths preferably forms a cluster to process bundled instructions. Each of the instruction paths has an array of pipelined execution units. Initially, two or more of the parallel instruction paths processes the same program thread (one or more bundles) through the execution units, but with different optimization characteristics set for each path. Assessment logic monitors the processing of the initial program thread through the execution units and selects the heuristics defining which path is in the lead. The other instruction paths are then reallocated, or synchronized, with the optimization characteristics of the lead instruction path, or with similarly optimized characteristics, to process other bundles of the program thread; preferably, the lead path continues processing of the initial thread without being disturbed. For other program thr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.