Silicide method for CMOS integrated circuits
US7029967B2 · kind B2 · utility
3Cited by
1References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Aug 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.