Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM
US7030012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | May 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.