Post ECP multi-step anneal/H2 treatment to reduce film impurity
US7030016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Mar 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.