Method of fabricating metal interconnection of semiconductor device
US7030021B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal layer through etching the metal layer; forming a pad electrically connecting the bottom metal layer to a scribe area; forming an insulating layer on the substrate including the bottom metal layer; forming a via hole and a trench, in which an upper metal layer is formed, on the insulating layer, the via hole connecting the bottom metal layer with the upper metal layer; forming a plating layer by means of electroplating; and performing a planarization process for the plating layer. Accordingly, the present invention needs not a separate seed layer because the bottom metal layer is used as a seed layer. In addition, the present invention can enhance device reliability by reducing electro-migration and stress-migration because the copper is uniformly grown from the bottom in one direction thereby completely filling the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.