Method for simultaneous degas and baking in copper damascene process
US7030023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Feb 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76873
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.