Power semiconductor component in the planar technique

US7030426B2 · kind B2 · utility

Assignee

• IXYS Semiconductor GmbH · DE

Inventor

• Arno Neidig · Plankstadt, DE

Key dates

• Filing date: Mar 14, 2005
• Grant date: Apr 18, 2006
• Expiry date: Mar 14, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/66

Abstract

In a power semiconductor component produced in a planar technique, a near-surface structure having at least one depression is formed in a surface region of an edge termination adjacent a main surface of the semiconductor body. The structure lies inside a space charge region formed when a voltage is applied at a junction between semiconductor regions of opposite conduction type. Dielectric material may fill the depression and form a passivation layer on the surface region. The depression may be an annular trench having a width to depth ratio ≦1. Alternatively, the structure may be waffle-shaped with multiple depressions.