Digital line delay using a single port memory
US7031206B2 · kind B2 · utility
0Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/01
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory (“RAM”) and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.