Digital multilevel memory system having multistage autozero sensing
US7031214B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.