Internal power management scheme for a memory chip in deep power down mode
US7031219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jun 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.