System and method for testing a memory
US7031866B1 · kind B1 · utility
8Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Dec 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.