Glitch-free memory address decoding circuits and methods and memory subsystems using the same
US7032083B1 · kind B1 · utility
4Cited by
1References
18Claims
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Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Mar 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.