Boundary scan apparatus and interconnect test method
US7032146B2 · kind B2 · utility
2Cited by
14References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.