Adaptive input logic for phase adjustments
US7034596B2 · kind B2 · utility
9Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Feb 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.