Partitioned source line architecture for ROM
US7035129B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM includes of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.