Inventor · New Delhi, IN

Amit Khanuja

14Patents

4h-index

17Co-inventors

53Inventor score

Filing activity: Apr 2, 2004 → Dec 23, 2020

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8837229B1	Circuit for generating negative bitline voltage	Electricity	10	Active
US9281030B2	Controlling timing of negative charge injection to generate reliable negative bitline voltage	Physics	9	Active
US7035129B1	Partitioned source line architecture for ROM	Physics	9	Expired
US9001569B1	Input trigger independent low leakage memory circuit	Physics	6	Active
US9842642B2	Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories	Physics	3	Active
US7301819B2	ROM with a partitioned source line architecture	Physics	3	Active
US8546251B1	Compact read only memory cell	Electricity	2	Active
US7376013B2	Compact virtual ground diffusion programmable ROM array architecture, system and method	Physics	1	Active
US8031542B2	Low leakage ROM architecture	Electricity	1	Active
US11302365B2	Area efficient and high-performance wordline segmented architecture	Physics	0	Active
US11574675B2	Temperature tracked dynamic keeper implementation to enable read operations	Physics	0	Active
US8031541B1	Low leakage ROM architecture	Physics	0	Active
US7929347B2	Compact virtual ground diffusion programmable ROM array architecture, system and method	Physics	0	Active
US7609550B2	Compact virtual ground diffusion programmable ROM array architecture, system and method	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.