Diode array architecture for addressing nanoscale resistive memory arrays
US7035141B1 · kind B1 · utility
85Cited by
1References
5Claims
0Family size
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Key dates
| Filing date | Nov 17, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Nov 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.