System and method for redundancy memory decoding
US7035152B1 · kind B1 · utility
10Cited by
38References
69Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Oct 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy system for disabling access to normal memory elements when memory addresses corresponding to those normal memory elements match programmed redundancy addresses before the memory addresses and the programmed redundancy addresses are compared. Access to the normal memory elements is disabled based on the programmed redundancy addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.