Delay locked loop circuit and its control method
US7035366B2 · kind B2 · utility
15Cited by
14References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 11, 2002 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Jul 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit comprising: a fundamental phase comparator for detecting a fundamental phase difference of two input signals; a delay circuit; a delay control circuit for adjusting a delay time of the delay circuit in response to an output signal of the fundamental phase comparator; and at least one further phase comparator for detecting a phase difference other than the fundamental phase difference such that an amount of change of the delay time is changed in accordance with the fundamental phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.