Asynchronous input/output cache having reduced latency
US7035981B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/303
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporane…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.