Memory arbiter with grace and ceiling periods and intelligent page gathering logic
US7035984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Mar 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.