Error correction coding and decoding in a solid-state storage device
US7036068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.