Automated processor generation system for designing a configurable processor and method for the same

US7036106B1 · kind B1 · utility

Assignee

• TENSILICA, INC. · US

Inventors

• Albert Ren-Rui Wang · Fremont, US
• Richard Ruddell · Los Gatos, US
• David William Goodwin · Sunnyvale, US
• Earl A. Killian · Los Altos Hills, US
• Nupur Bhattacharyya · Mountain View, US
• Marines Puig Medina · San Jose, US
• Walter D. Lichtenstein · Belmont, US
• Pavlos Konas · Mountain View, US
• Rangarajan Srinivasan · Los Gatos, US
• Christopher Mark Songer · San Jose, US
• Akilesh Parameswar · San Jose, US
• Dror Maydan · Palo Alto, US
• Ricardo E. Gonzalez · Menlo Park, US

Key dates

• Filing date: Feb 17, 2000
• Grant date: Apr 25, 2006
• Expiry date: Feb 17, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/30
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.