Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell
US7037786B2 · kind B2 · utility
0Cited by
7References
22Claims
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Key dates
| Filing date | Nov 18, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Feb 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
Abstract
A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps needed to form the devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.