Independently accessed double-gate and tri-gate transistors in same process flow
US7037790B2 · kind B2 · utility
120Cited by
16References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2005 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | May 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.