Method for sharing configuration data for high logic density on chip
US7038489B2 · kind B2 · utility
2Cited by
5References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | May 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.