Soft-error rate hardened pulsed latch
US7038515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Dec 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.