Circuit for determining the time difference between edges of a first digital signal and of a second digital signal
US7039143B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Sep 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M) for storing the signal level which is applied to the input of the basic element, and the output of a storage element (M) is connected to the input of a next basic element. Furthermore, the circuit has a second input for supplying a second signal (S2) which is connected to a control input of each basic element. Given a first level of the second signal, the storage elements (M) take up the signal level stored in the preceding storage element, and given a second level of the second signal, the storage elements (M) retain the signal level respectively stored in them. Furthermore, the circuit has comparator units (XOR) to which, in each case, the signal levels stored by the storage units (M) of two adjacent basic elements are supplied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.