Low leakage SRAM scheme
US7039818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Jun 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.