On-chip reset circuitry and method
US7039823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.