Alan Hales
25Patents
7h-index
13Co-inventors
62Inventor score
Filing activity: Nov 22, 2002 → Jul 9, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6894308B2 | IC with comparator receiving expected and mask data from pads | Physics | 35 | Expired |
| US8205125B2 | Enhanced control in scan tests of integrated circuits with partitioned scan chains | Physics | 30 | Active |
| US7842949B2 | IC with comparator receiving expected and mask data from pads | Physics | 10 | Active |
| US7491970B2 | IC with comparator receiving expected and mask data from pads | Physics | 9 | Active |
| US7655946B2 | IC with comparator receiving expected and mask data from pads | Physics | 8 | Active |
| US8525565B2 | Family of multiplexer/flip-flops with enhanced testability | Electricity | 8 | Active |
| US8299464B2 | Comparator receiving expected and mask data from circuit pads | Physics | 8 | Active |
| US7469372B2 | Scan sequenced power-on initialization | Physics | 6 | Active |
| US8375265B1 | Delay fault testing using distributed clock dividers | Physics | 5 | Active |
| US7183570B2 | IC with comparator receiving expected and mask data from pads | Physics | 4 | Expired |
| US7039823B2 | On-chip reset circuitry and method | Physics | 2 | Expired |
| US8872178B2 | IC with comparator receiving expected and mask data from pads | Physics | 1 | Active |
| US10120025B2 | Functional core circuitry with serial scan test expected, mask circuitry | Physics | 1 | Active |
| US9562946B2 | Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads | Physics | 1 | Active |
| US9322879B2 | Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads | Physics | 1 | Active |
| US9103885B2 | Integrated circuit with plural comparators receiving expected data and mask data from different pads | Physics | 0 | Active |
| US7389455B2 | Register file initialization to prevent unknown outputs during test | Physics | 0 | Active |
| US11092650B2 | Re-programmable self-test | Physics | 0 | Active |
| US8692248B2 | Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry | Physics | 0 | Active |
| US9702935B2 | Packet based integrated circuit testing | Physics | 0 | Active |
| US8397112B2 | Test chain testability in a system for testing tri-state functionality | Physics | 0 | Active |
| US8604475B2 | IC dies with serarate connections to expected and mask data | Physics | 0 | Active |
| US9829538B2 | IC expected data and mask data on I/O data pads | Physics | 0 | Active |
| US11768240B2 | Re-programmable self-test | Physics | 0 | Active |
| US10247780B2 | Re-programmable self-test | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.