Floating gate memory device and method of manufacturing the same
US7041558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530° C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580° C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.