Integrated memory circuit for storing a binary datum in a memory cell
US7042039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Nov 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/08
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.