Semiconductor package and method of manufacturing the same which reduces warpage
US7042072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Aug 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.