Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays
US7042779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jun 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.