Semiconductor memory device for reducing write recovery time
US7042781B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for reducing a data recovery time includes a cell block having a plurality of unit cells, each for storing a data; a command control block for receiving an activation control signal and a precharge command signal to thereby generate first and second control signals; an overdriving control block for generating a control pulse in response to the first control signal; a power supplier for selectively supplying one of a core voltage and a high voltage in response to the control pulse; and a sense amplifying block, which is enabled by the second control signal, for sensing and amplifying the data stored in the cell block by using one of the core voltage and the high voltage outputted from the power supplier, wherein an activation period of the second control signal is longer than that of the first control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.