High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory

US7043417B1 · kind B1 · utility

Assignee

• Quickturn Design Systems, Inc. · US

Inventors

• William F. Beausoleil · Hopewell Junction, US
• R. Bryan Cook · Poughkeepsie, US
• Tak-kwong Ng · Yorktown, US
• Helmut Roth · Stuttgart, DE
• Peter Tannenbaum · Red Hook, US
• Lawrence A. Thomas · West Hurley, US
• Norton J. Tomassetti · Kingston, US

Key dates

• Filing date: Sep 6, 2000
• Grant date: May 9, 2006
• Expiry date: Jun 7, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1647
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.