Piggybacking of ECC corrections behind loads
US7043679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Nov 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.