System and method for defining semiconductor device layout parameters
US7043711B2 · kind B2 · utility
1Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jun 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device is disclosed. The method allows a customer to create a partial layout of the semiconductor device based on a first set of rules, and then allows a manufacturer to generate a more complete layout of the semiconductor device based on the partial layout and the second set of rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.