JFET and MESFET structures for low voltage high current and high frequency applications
US7045397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2005 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.