Amorphous etch stop for the anisotropic etching of substrates
US7045407B2 · kind B2 · utility
111Cited by
8References
7Claims
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Key dates
| Filing date | Dec 30, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.