MOS transistor gates with thin lower metal silicide and methods for making the same
US7045456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.