Semiconductor device including a superlattice with regions defining a semiconductor junction
US7045813B2 · kind B2 · utility
107Cited by
37References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 1, 2005 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Apr 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/07
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.