Semiconductor wafer comprising micro-machined components
US7045869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2004 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Aug 27, 2024 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/019
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor wafer having a matrix array of micro-mirrors comprises a component substrate carried on a base substrate. The component substrate comprises a membrane layer in which the micro-mirrors are formed and a supporting handle layer. The base substrate comprises a base layer from which a plurality of pedestals extend upwardly therefrom into cavities in the handle layer corresponding to the micro-mirrors. Each pedestal carries electrodes for co-operating with the micro-mirrors for tilting thereof. Conductors through vias in the pedestals connect the electrodes to electrically conductive tracks on a bottom surface, and in turn through conductors through vias to addressing terminals for addressing the electrodes. By forming the pedestals in the base substrate and projecting the pedestals into the cavities in the handle layer the handle layer is recessed into the base substrate thereby facilitating the provision of a handle layer of depth sufficient for adequately supporting the membrane layer during fabrication of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.