Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer
US7045896B2 · kind B2 · utility
16Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.