System with dual rail regulated locked loop
US7046056B2 · kind B2 · utility
26Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2005 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Apr 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.