Benedict Lau
100Patents
25h-index
35Co-inventors
90Inventor score
Filing activity: Feb 6, 1997 → Nov 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6643787B1 | Bus system optimization | Electricity | 313 | Expired |
| US6125157A | Delay-locked loop circuitry for clock delay adjustment | Electricity | 250 | Expired |
| US6047346A | System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers | Physics | 195 | Expired |
| US6539072B1 | Delay locked loop circuitry for clock delay adjustment | Electricity | 169 | Expired |
| US6950956B2 | Integrated circuit with timing adjustment mechanism and method | Electricity | 132 | Expired |
| US6133773A | Variable delay element | Electricity | 104 | Expired |
| US6924660B2 | Calibration methods and circuits for optimized on-die termination | Electricity | 100 | Expired |
| US7042914B2 | Calibrated data communication system and method | Electricity | 77 | Expired |
| US6469555B1 | Apparatus and method for generating multiple clock signals from a single loop circuit | Electricity | 74 | Expired |
| US6509756B1 | Method and apparatus for low capacitance, high output impedance driver | Physics | 66 | Expired |
| US6369652B1 | Differential amplifiers with current and resistance compensation elements for balanced output | Electricity | 64 | Expired |
| US6759881B2 | System with phase jumping locked loop circuit | Electricity | 61 | Expired |
| US6462588B2 | Asymmetry control for an output driver | Electricity | 60 | Expired |
| US7151390B2 | Calibration methods and circuits for optimized on-die termination | Electricity | 55 | Expired |
| US6806728B2 | Circuit and method for interfacing to a bus channel | Physics | 54 | Expired |
| US7535933B2 | Calibrated data communication system and method | Electricity | 53 | Active |
| US6760857B1 | System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively | Physics | 52 | Expired |
| US7307461B2 | System and method for adaptive duty cycle optimization | Physics | 37 | Expired |
| US6897699B1 | Clock distribution network with process, supply-voltage, and temperature compensation | Electricity | 33 | Expired |
| US7133945B2 | Scalable I/O signaling topology using source-calibrated reference voltages | Electricity | 30 | Expired |
| US6911853B2 | Locked loop with dual rail regulation | Electricity | 30 | Expired |
| US7543172B2 | Strobe masking in a signaling system having multiple clock domains | Physics | 28 | Expired |
| US7321524B2 | Memory controller with staggered request signal output | Physics | 27 | Expired |
| US6330193A | Method and apparatus for low capacitance, high output impedance driver | Physics | 26 | Expired |
| US7046056B2 | System with dual rail regulated locked loop | Electricity | 26 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.