SRAM cell with read-disturb immunity
US7046544B1 · kind B1 · utility
9Cited by
5References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Feb 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are small, efficient SRAM cells that are insensitive to read errors. SRAM cells in accordance with one embodiment include a pair of cross-coupled inverters extending between first and second bit nodes and a read amplifier extending from one of the first and second bit nodes to an associated bitline. During a read access to a given memory cell, the corresponding read amplifier isolates the bit nodes from the bitlines to prevent the voltage on bitline BL from disturbing data stored in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.