Method for producing test patterns for testing an integrated circuit
US7047174B2 · kind B2 · utility
5Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2001 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3183
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.