Testing methodology and apparatus for interconnects
US7047458B2 · kind B2 · utility
15Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Nov 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.